aimlroles

Infrastructure AI/ML Engineer for Memory Design, Characterization, and Yield Optimization

Broadcom Open · verified Oct 22, 2026
USA-TX-Austin - River Place B7 Full-time Mid-level Machine Learning Engineering

At a glance

Mid-level Machine Learning Engineering role at Broadcom. USA-TX-Austin - River Place B7 · full-time · $150,800–$241,200 base.

SalaryStated by Broadcom
$150,800 – $241,200
Base salary for this role, in USD per year, as published in the posting.
RoleMachine Learning Engineering
SeniorityMid-level
LocationUSA-TX-Austin - River Place B7
EmploymentFull-time
Base pay$150,800–$241,200
PostedOct 14, 2026 · 8d ago
Role brief

aimlroles summary, based on the employer's posting.

What you'll do

  • Design and scale distributed agent systems that improve embedded-memory workflows for performance, power, area and yield
  • Coordinate autonomous agents across memory development, silicon bring-up and yield investigations, breaking work into steps and decisions
  • Link LLM-based agent processes with EDA platforms, internal engineering software and enterprise data stores
  • Build ML classifiers for scan-chain failures and relate their results to DFT structures; use fab, PCM and E-test data to flag yield risks
  • Turn memory engineering practices into modular agent workflows with design, EDA and infrastructure colleagues, aligned to technical milestones

What you bring

  • At least fifteen years spanning memory engineering, DFT, silicon yield work, software architecture and AI systems development
  • A graduate degree in electrical engineering or computer engineering, at master’s or doctoral level
  • Experience with embedded-memory design and characterization on advanced process nodes, plus compute-in-memory architecture
  • Production LLM application work covering agent coordination, tool calling and retrieval, with LangGraph and MCP experience
  • Strong Python and TCL skills, alongside chip-design and verification knowledge and experience testing safeguards for AI systems

Who this fits

This position suits an experienced engineer combining memory design and silicon-yield knowledge with production AI infrastructure skills. It calls for at least fifteen years of relevant experience and a master’s or Ph.D. in electrical or computer engineering.

From the employer

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Job Description:

Infrastructure AI/ML Engineer for Memory Design, Characterization,

and Yield Optimization


Job Description

The Central Engineering Group is seeking an energetic, visionary, and passionate Infrastructure AI/ ML Engineer to lead the Agentic AI Infrastructure development workflow for memory design, characterization, and yield optimization.


In this role, you will collaborate with memory designers and DFT experts to build Agentic AI workflows that drive the development of state-of-the-art embedded memories optimized for PPA, DFT, and yield.


Minimum Education & Experience Qualifications

● Experience: 15+ years of progressive, relevant experience in Memory design, DFT, Silicon Yield Analysis, software architecture and AI systems engineering.

● Education: Master’s degree or Ph.D. in Electrical Engineering or Computer Engineering.


Key Job Responsibilities

● Conceptualize, architect, deploy, and scale robust, distributed multi-agent AI frameworks tailored to transform intricate memory design workflows optimized for performance, power, area, and yield

● Orchestrate long-horizon, autonomous agent executions capable of managing multi-step reasoning, task decomposition, and decision-making across all phases of memory design development, silicon bring-up, and yield analysis

● Seamlessly integrate Large Language Model (LLM)-driven agent pipelines with core Electronic Design Automation (EDA) suites, custom in-house software tools, and enterprise data repositories.

● AI-Driven Debug: Develop and deploy ML models to automate the classification of scan failures (Chain, Stuck-at, Transition) and correlate them with design-for-test (DFT) structures.

● Predictive Yield Modeling: Integrate high-dimensional data—including Fab process parameters, PCM (Process Control Monitoring), and E-test data—to predict yield excursions before they hit the assembly line.

● Partner collaboratively with Memory Design Leads, EDA Tool Specialists, and Infrastructure Engineers to distill complex, domain-specific hardware engineering methodologies into modular, goal-driven agentic workflows.

● Align AI workflow capabilities directly with organizational efficiency targets and technical milestones across the Central Engineering Group.


Required Skillset & Technical Competencies

● Memory Design, Characterization and Yield Analysis:

● Experience designing and characterizing embedded memory in advanced technology process nodes

● Experience in compute-in-memory design and architecture

● AI Engineering & Multi-Agent Expertise:

● Experience architecting production-grade LLM applications: multi-agent orchestration,

function-calling/tool-use, and retrieval-augmented generation (RAG).

● Experience integrating agentic systems with enterprise tools, services, and knowledge sources – including building and consuming Model Context Protocol (MCP) servers, and packaging reusable agent capabilities (e.g., Agent Skills).

● Deep experience with agent orchestration frameworks such as LangGraph.

● Semiconductor Domain Knowledge & EDA Tooling:

● Fundamental grasp of chip design methodologies, IP block development lifecycles, and verification environments.

● Hands-on familiarity with industry-standard EDA tooling and frameworks

from Synopsys, Cadence, and Siemens EDA, alongside System Verilog & UVM verification environments.

● Software Engineering & Infrastructure Mastery:

● High proficiency in core programming languages and system design concepts, specifically Python and TCL.

● Expertise in microservices architecture, REST APIs, Docker, Kubernetes, Sandboxing, and config-driven workflow orchestration engine design.

● AI System Verification & Data Engineering:

● Proven experience establishing evaluation metrics, testing benchmarks, and safety guardrails for non-deterministic AI systems in high-stakes environments.

● Technical depth in Vector Databases, and cloud-native containerized orchestration pipelines.


Compensation and Benefits


The annual base salary range for this position is USD 150,800.00 To USD 241,200.00

As a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company's growth. All subject to relevant plan documents and award agreements.


Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.


Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.


If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.